Variations in semiconductor wafer processing typically introduce defects and unpredictable parametric variations (e.g., excessive current draw) into traditional memory technologies. Such variations generally affect the reliability of memory devices. Some conventional memory architectures include circuitry to improve reliability of memory devices over fluctuations in process. In one approach, programmable circuitry is used to reduce the effects of process variations on memory operations in conventional memory technologies, which includes transistor or gated-based memories (e.g., DRAM, Flash, etc.). While such circuitry is functional, the conventional techniques of reducing the effects of process variations are not well suited for advanced memory technologies. For example, in conventional memory architectures, the memory cells are formed in a single plane, which inherently provides for a uniform formation of semiconductor structures over a two-dimensional plane. Thus, the common techniques for improving program, read and erase operations in connection with conventional memory cells are not well-suited for fine-tuning memory operations in other memory technologies.
It would be desirable to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional memory architectures to compensate for parameter variations associated with the operation of memory cells, for example, in a cross-point memory array with multiple layers of memory.
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